1. Field of the Invention
The present invention relates to the manufacture and design of a self-aligned transistor for use in vertical storage cells, especially transistors for use in dynamic random access memory (DRAM) cells and advanced memory devices containing the same. Specifically, the memory cell of the present invention uses a vertical thin film transistor (TFT) created in a self-aligned process over the trench storage node.
2. Background of the Invention
Generally, a semiconductor memory device such as a dynamic random access memory (DRAM) chip comprises a plurality of memory cells which are used to store a large quantity of information. Each memory cell includes a capacitor for storing electric charge and a transistor for opening and closing charge and discharge passages of the capacitor. The number of bits on DRAM chips has been increasing by approximately 4xc3x97 every three years; this increase has been achieved through improvements in photolithographic techniques used to fabricate chips and innovations in cell design.
Among the first of these innovations was the use of three dimensional cell structures that utilized area above the silicon surface (stacked capacitor) or below the silicon surface (trench capacitor) for the storage capacitor. Since their introduction with the 4 M generation, trench capacitor innovations have kept pace with lithographic improvements. This has been accomplished largely by making structural changes inside the storage trench.
However, 64 M DRAM contained little cell structure innovation, hence DRAM cell size has not decreased in the same historical rate from the preceding 16 M generation. This has led to a larger chip and lower productivity of the 64 M DRAM cell than was predicted. The same trend is extending out through 256 M. In order to achieve acceptable cell size, new structures must be developed which require only 4 lithographic squares compared to current 8 square cells.
The present invention provides a memory cell such as a DRAM which requires only 4 lithographic squares to fabricate thereby significantly reducing the size of the memory cell compared to past generations wherein 8 lithographic squares were required in fabricating the same.
The present invention further provides a memory cell wherein the transistor of the cell is a thin film transistor (TFT) which is self-aligned to the trench storage node.
One aspect of the present invention is directed to a method of fabricating a memory cell, e.g. DRAM, having a thin film transistor self-aligned with the trench storage node. Such a method provides a memory cell having reduced cell size, and more importantly, the new cell design of the present invention has a high productivity associated therewith. Specifically, the method of the present invention comprises the steps of:
(a) providing a substrate, said substrate having a dielectric stack formed on a surface thereof;
(b) forming a vertical trench in said dielectric stack and said substrate;
(c) forming a capacitor node in said vertical trench, said capacitor node occupying a horizontal capacitor area; and
(d) forming a transistor above said capacitor node, said transistor occupying a horizontal device area substantially equal to that of the horizontal capacitor area.
Step (d) above includes forming each of the following: a gate near the periphery of the horizontal device area; an oxide layer on an inside surface of the gate; a conductive body inside the oxide layer, said conductive body having a top surface and a bottom surface; and diffusion regions in the conductive body near the top and bottom surfaces.
The method of the present invention further includes the steps of forming a bitline coupled to the conductive body of the cell and forming a wordline that is coupled to the gate.
Another aspect of the present invention relates to a memory cell that is produced using the above self-aligned processing steps. Specifically, the memory cell of the present invention comprises: a substrate having a top surface; a capacitor extending vertically into the substrate for storing a voltage representing a datum, said capacitor occupying a geometrically shaped horizontal area; a transistor formed above the capacitor and occupying a horizontal area substantially equal to the geometrically shaped horizontal area, and having a vertical device depth, for establishing an electrical connection with the capacitor, in response to a control signal, for reading from, and writing to, the capacitor, wherein the transistor includes a gate formed near the periphery of said horizontal device area and having a vertical depth approximately equal to the vertical device depth; an oxide layer on an inside surface of the gate; a conductive body formed inside the oxide layer, said conductive body having a top surface and a bottom surface and a vertical depth approximately equal to the vertical device depth; and diffusion regions in the conductive body near the top and bottom surfaces.
The above described memory cell further comprises a bitline coupled to the gate for providing a voltage representing a datum and a wordline coupled to the gate for providing the control signal.
A further aspect of the present invention relates to a vertical self-aligned thin film transistor who""s body is fully depleted. That is, a transistor in which the conductive body lacks excess carriers to transport a current. The fully depleted state is caused by applying a bias voltage to the gate area that surrounds the transistor such that an electric field is created that is capable of depleting the conductive body. In this state, the device is turned off.
Specifically, the vertical self-aligned thin film transistor of the present invention comprises a gate formed near the periphery of a horizontal device area and having a depth approximately equal to a vertical device depth; an oxide layer on an inside surface of the gate; a conductive body formed inside the oxide layer, said conductive body having a top surface and a bottom surface and a vertical depth approximately equal to the vertical device depth; and diffusion regions in the body near the top and bottom surfaces, wherein said conductive body is fully depleted.